Date : 12th March,2014
Today I learned about RISC(Reduced Instruction Set Computer)
Here I would like to share about some of the Interesting facts that I learned about RISC:
1)The development of high level language give rise to a problem called Semantic gap(the difference between the operations provided in HLL and that provided in Computer architecture)
2)To reduce the gap between HLL and the instruction set of computer
architecture, the system becomes more and more complex and the resulted
system is termed as
Complex Instruction Set Computer (CISC).
3)So to reduce the complexity,a most interesting and important processor architecture evolves which is
termed as Reduced Instruction Set Computer (RISC) architecture.
4)Characteristics of Reduced Instruction Set Architecture are as follows:
a)One Machine Instruction per Machine Cycle.
b)Register to Register Operations
c)Simple Addressing modes
d)Simple Instruction Format
Design Issues of RISC:
A strategy is needed that will allow the most frequently accessed
operands to be kept in registers and to minimize register-memory
operations.
So there are two approaches.So, they are as follows:
- The software approach is to rely on the
compiler to maximize register uses. The compiler will attempt to
allocate registers to those variables that will be used the most in a
given time period.
- The hardware approach is simply to use more registers so that more variables can be held in registers for longer period of time.
As far as Software Approach is concerned, it is totally the responsibility of compiler to optimize the register usage.The task of optimization is to decide which quantities are to be
assigned to registers at any given point of time in the program. The
technique most commonly used in RISC compiler is known as
graph coloring.
Given a graph
consisting of nodes and edges, assign colors to nodes such that adjacent
nodes have different colors, and do this in such a way as to minimize
the number of different colors.
This graph coloring problem is mapped to the register optimization problem of the compiler in the following way:
- The program is analyzed to build a register interference graph.
- The nodes of the graph are the symbolic registers.
- If two symbolic registers are “live” during the same program fragment, then they are joined by an edge to indicate interference.
- An attempt is then made to color the graph with n colors, where n is the number of register.
- Nodes that cannot be colored are placed in memory.
- Load and store must be used to make space for the affected quantities when they are needed.
